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mos integrated circuit m PD42S17405L, 4217405l 3.3 v operation 16 m-bit dynamic ram 4 m-word by 4-bit, edo the mark shows major revised points. document no. m10068ej6v0ds00 (6th edition) date published january 1997 n printed in japan description the m PD42S17405L, 4217405l are 4,194,304 words by 4 bits cmos dynamic rams with optional edo. edo is a kind of the page mode and is useful for the read operation. besides, the m PD42S17405L can execute cas before ras self refresh. the m PD42S17405L, 4217405l are packaged in 26-pin plastic tsop (ii) and 26-pin plastic soj. features ? edo (hyper page mode) ? 4,194,304 words by 4 bits organization ? single +3.3 v 0.3 v power supply ? fast access and cycle time power access time r/w cycle time edo (hyper page mode) part number consumption (max.) (min.) active (max.) cycle time (min.) m PD42S17405L-a50, 4217405l-a50 660 mw 50 ns 84 ns 20 ns m PD42S17405L-a60, 4217405l-a60 360 mw 60 ns 104 ns 25 ns m PD42S17405L-a70, 4217405l-a70 324 mw 70 ns 124 ns 30 ns ? m PD42S17405L can execute cas before ras self refresh part number refresh cycle refresh power consumption at standby (max.) m PD42S17405L 2,048 cycles/128 ms cas before ras self refresh 0.54 mw cas before ras refresh (cmos level input) ras only refresh hidden refresh m pd4217405l 2,048 cycles/32 ms cas before ras refresh 1.8 mw ras only refresh (cmos level input) hidden refresh the information in this document is subject to change without notice. 1995 data sheet
m PD42S17405L, 4217405l 2 ordering information part number access time package refresh (max.) m PD42S17405Lg3-a50-7jd 50 ns m PD42S17405Lg3-a60-7jd 60 ns m PD42S17405Lg3-a70-7jd 70 ns m PD42S17405Lla-a50 50 ns m PD42S17405Lla-a60 60 ns m PD42S17405Lla-a70 70 ns m pd4217405lg3-a50-7jd 50 ns m pd4217405lg3-a60-7jd 60 ns m pd4217405lg3-a70-7jd 70 ns m pd4217405lla-a50 50 ns m pd4217405lla-a60 60 ns m pd4217405lla-a70 70 ns cas before ras self refresh cas before ras refresh ras only refresh hidden refresh 26-pin plastic tsop (ii) (300 mil) 26-pin plastic soj (300 mil) 26-pin plastic tsop (ii) (300 mil) 26-pin plastic soj (300 mil) cas before ras refresh ras only refresh hidden refresh
m PD42S17405L, 4217405l 3 pin configurations (marking side) 26-pin plastic tsop (ii) (300 mil) 26-pin plastic soj (300 mil) a0 to a10 : address inputs i/o1 to i/o4: data inputs/outputs ras : row address strobe cas : column address strobe we : write enable oe : output enable v cc : power supply gnd : ground nc : no connection gnd i/o4 i/o3 cas oe 26 25 24 23 22 a8 a7 a6 a5 a4 18 17 16 15 14 v cc i/o1 i/o2 we ras 1 2 3 4 5 9 10 11 12 13 a0 a1 a2 a3 v cc PD42S17405Lg3-7jd m nc 6 a9 21 19 8 a10 gnd pd4217405lg3-7jd m gnd i/o4 i/o3 cas oe 26 25 24 23 22 a8 a7 a6 a5 a4 18 17 16 15 14 v cc i/o1 i/o2 we ras 1 2 3 4 5 9 10 11 12 13 a0 a1 a2 a3 v cc PD42S17405Lla m nc 6 a9 21 19 8 a10 gnd pd4217405lla m
m PD42S17405L, 4217405l 4 block diagram clock generator cas before ras counter ras cas we v cc gnd a0 to a10 x0 - x10 y0 - y10 row decoder row address buffer column address buffer 2,048 memory cell array 2,048 2,048 4 2,048 4 2,048 sense amplifier column decoder 4 oe i/o1 to i/o4 data output buffer data input buffer
m PD42S17405L, 4217405l 5 input/output pin functions the m PD42S17405L, 4217405l have input pins ras, cas, we, oe, a0 to a10 and input/output pins i/o1 to i/o4. pin name ras (row address strobe) cas (column address strobe) a0 to a10 (address inputs) we (write enable) oe (output enable) i/o1 to i/o4 (data inputs/outputs) input/output function input ras activates the sense amplifier by latching a row address and selecting a corresponding word line. it refreshes memory cell array of one line selected by the row address. it also selects the following function. ? cas before ras refresh input cas activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. input address bus. input total 22-bit of address signal, upper 11-bit and lower 11-bit in sequence (address multiplex method). therefore, one word is selected from 4,194,304-word by 4-bit memory cell array. in actual operation, latch row address by specifying row address and activating ras. then, switch the address bus to column address and activate cas. each address is taken into the device when ras and cas are activated. therefore, the address input setup time (t asr , t asc ) and hold time (t rah , t cah ) are specified for the activation of ras and cas. input write control signal. write operation is executed by activating ras, cas and we. input read control signal. read operation can be executed by activating ras, cas and oe. if we is activated during read operation, oe is to be ineffective in the device. therefore, read operation cannot be executed. input/output 4-bit data bus. i/o1 to i/o4 are used to input/output data.
m PD42S17405L, 4217405l 6 hyper page mode (edo) the hyper page mode (edo) is a kind of page mode with enhanced features. the two major features of the hyper page mode (edo) are as follows. 1. data output time is extended. in the hyper page mode (edo), the output data is held to the next cas cycles falling edge, instead of the rising edge. for this reason, valid data output time in the hyper page mode (edo) is extended compared with the fast page mode (= data extend function). in the fast page mode, the data output time becomes shorter as the cas cycle time becomes shorter. therefore, in the hyper page mode (edo), the timing margin in read cycle is larger than that of the fast page mode even if the cas cycle time becomes shorter. 2. the cas cycle time in the hyper page mode (edo) is shorter than that in the fast page mode. in the hyper page mode (edo), due to the data extend function, the cas cycle time can be shorter than in the fast page mode if the timing margin is the same. taking a device whose t rac is 60 ns as an example, the cas cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns. in the hyper page mode (edo), read (data out) and write (data in) cycles can be executed repeatedly during one ras cycle. the hyper page mode (edo) allows both read and write operations during one cycle. the following shows a part of the hyper page mode (edo) read cycle. specifications to be observed are described in the next page. hyper page mode (edo) read cycle t hpc t oea t oez t aa hi - z hi - z row col.a col.b col.c t oea t olz ras v ih v il cas v ih v il address v ih v il v ih v il oe v ih v il i/o v oh v ol data out a data out b data out c data out c t oez t aa t cac t oez t oep t oep t och t cho t cho we t rac t aa t cac t clz t cac t clz t wpz t dhc t ofc t ofr t wez t och t rrh t rch
m PD42S17405L, 4217405l 7 cautions when using the hyper page mode (edo) 1. cas access should be used to operate t hpc at the min. value. 2. to make i/os to hi-z in read cycle, it is necessary to control ras, cas, we, oe as follows. the effective specification depends on the state of each signal. (1) both ras and cas are inactive (at the end of read cycle) we: inactive, oe: active t ofc is effective when ras is inactivated before cas is inactivated. t ofr is effective when cas is inactivated before ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both ras and cas are active or either ras or cas is active (in read cycle) we, oe: inactive t oez is effective. both ras and cas are inactive or ras is active and cas is inactive (at the end of read cycle) we, oe: active and either t rrh or t rch must be met t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective. 3. in read cycle, the effective specification depends on the state of cas signal when controlling data output with the oe signal. (1) cas: inactive, oe: active t cho is effective. (2) cas, oe: active t och is effective.
m PD42S17405L, 4217405l 8 electrical specifications ? all voltages are referenced to gnd. ? after power up (v cc 3 v cc (min.) ), wait more than 100 m s (ras, cas inactive) and then, execute eight cas before ras or ras only refresh cycles as dummy cycles to initialize internal circuit. absolute maximum ratings parameter symbol condition rating unit voltage on any pin relative to gnd v t C0.5 to +4.6 v supply voltage v cc C0.5 to +4.6 v output current i o 20 ma power dissipation p d 1w operating ambient temperature t a 0 to +70 ?c storage temperature t stg C55 to +125 ?c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 +0.8 v operating ambient temperature t a 070?c capacitance (t a = 25 ?c, f = 1 mh z ) parameter symbol test condition min. typ. max. unit input capacitance c i1 address 5 pf c i2 ras, cas, we, oe 7 data input/output capacitance c i/o i/o 7 pf
m PD42S17405L, 4217405l 9 t rc = t rc (min.) , i o = 0 ma ras, cas cycling t rc = t rc (min.) , i o = 0 ma standby current cas before ras refresh current cas before ras refresh: t rc = 62.5 m s ras, cas: v cc C 0.2 v v ih v ih (max.) 0 v v il 0.2 v standby: ras, cas 3 v cc C 0.2 v address: v ih or v il we, oe: v ih i o = 0 ma ras, cas: t rass = 5 ms v cc C 0.2 v v ih v ih (max.) 0 v v il 0.2 v i o = 0 ma notes 1. i cc1 , i cc3 , i cc4 , i cc5 and i cc6 depend on cycle rates (t rc and t hpc ). 2. specified values are obtained with outputs unloaded. 3. i cc1 and i cc3 are measured assuming that address can be changed once or less during ras v il (max.) and cas 3 v ih (min.) . 4. i cc3 is measured assuming that all column address inputs are held at either high or low. 5. i cc4 is measured assuming that all column address inputs are switched only once during each hyper page (edo) cycle. dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 t rac = 50 ns 120 ma 1, 2, 3 t rac = 60 ns 100 t rac = 70 ns 90 m PD42S17405L i cc2 ras, cas 3 v ih (min.) , i o = 0 ma 0.5 ma ras, cas 3 v cc C 0.2 v, i o = 0 ma 0.15 m pd4217405l ras, cas 3 v ih (min.) , i o = 0 ma 2.0 ras, cas 3 v cc C 0.2 v, i o = 0 ma 0.5 ras only refresh current i cc3 t rac = 50 ns 120 ma 1, 2, 3 ,4 t rac = 60 ns 100 t rac = 70 ns 90 i cc4 t rac = 50 ns 100 ma 1, 2, 5 t rac = 60 ns 90 t rac = 70 ns 80 i cc5 t rac = 50 ns 120 ma 1, 2 t rac = 60 ns 100 t rac = 70 ns 90 i cc6 t ras 300 ns 400 m a 1, 2 t ras 1 m s 450 m a 1, 2 i cc7 200 m a2 input leakage current i i (l) v i = 0 to 3.6 v C5 +5 m a all other pins not under test = 0 v output leakage current i o (l) v o = 0 to 3.6 v C5 +5 m a output is disabled (hi-z) high level output voltage v oh i o = C2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v ras cycling, cas 3 v ih (min.) ras v il (max.) , cas cycling t hpc = t hpc (min.) , i o = 0 ma ras cycling t rc = t rc (min.) , i o = 0 ma operating current (hyper page mode (edo)) cas before ras long refresh current (2,048 cycles / 128 ms, only for the m PD42S17405L) cas before ras self refresh current (only for the m PD42S17405L)
m PD42S17405L, 4217405l 10 ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions (1) input timing specification (2) output timing specification v ih (min.) = 2.0 v v il (max.) = 0.8 v v oh (min.) = 2.0 v v ol (max.) = 0.8 v t t = 2 ns t t = 2 ns (3) output load condition 100 pf c l i/o 1,180 w 870 w v cc common to read, write, read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit notes min. max. min. max. min. max. read / write cycle time t rc 84 C 104 C 124 C ns ras precharge time t rp 30 C 40 C 50 C ns cas precharge time t cpn 7 C 10 C 10 C ns ras pulse width t ras 50 10,000 60 10,000 70 10,000 ns 1 cas pulse width t cas 7 10,000 10 10,000 12 10,000 ns ras hold time t rsh 10 C 15 C 20 C ns cas hold time t csh 38 C 45 C 50 C ns ras to cas delay time t rcd 11 37 14 45 14 52 ns 2 ras to column address delay time t rad 9 2512301235ns2 cas to ras precharge time t crp 5C5C5Cns3 row address setup time t asr 0C0C0Cns row address hold time t rah 7 C 10 C 10 C ns column address setup time t asc 0C0C0Cns column address hold time t cah 7 C 10 C 12 C ns oe lead time referenced to ras t oes 0C0C0Cns cas to data setup time t clz 0C0C0Cns oe to data setup time t olz 0C0C0Cns oe to data delay time t oed 10 C 13 C 15 C ns transition time (rise and fall) t t 150150150ns refresh time m PD42S17405L t ref C 128 C 128 C 128 ms 4 m pd4217405l C 32 C 32 C 32
m PD42S17405L, 4217405l 11 notes 1. in cas before ras refresh cycles, t ras (max.) is 100 m s. if 10 m s < t ras < 100 m s, ras precharge time for cas before ras self refresh (t rps ) is applied. 2. for read cycles, access time is defined as follows: input conditions access time access time from ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only ; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 3. t crp (min.) requirement is applied to ras, cas cycles. 4. this specification is applied only to the m PD42S17405L. read cycle parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit notes min. max. min. max. min. max. access time from ras t rac C50C60C70ns1 access time from cas t cac C13C15C18ns1 access time from column address t aa C25C30C35ns1 access time from oe t oea C13C15C18ns column address lead time referenced to ras t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time referenced to ras t rrh 0C0C0Cns2 read command hold time referenced to cas t rch 0C0C0Cns2 output buffer turn-off delay time from oe t oez 010013015ns3 cas hold time to oe t cho 5C5C5Cns4 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. either t rch (min.) or t rrh (min.) should be met in read cycles. 3. t oez(max.) defines the time when the output achieves the condition of hi-z and is not referenced to v oh or v ol . 4. we: inactive (in read cycle) cas: inactive, oe: active t cho is effective. cas, oe: active t och is effective.
m PD42S17405L, 4217405l 12 write cycle parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit notes min. max. min. max. min. max. we hold time referenced to cas t wch 7 C 10 C 10 C ns 1 we pulse width t wp 7 C 10 C 10 C ns 1 we lead time referenced to ras t rwl 10 C 15 C 20 C ns we lead time referenced to cas t cwl 7 C 10 C 12 C ns we setup time t wcs 0C0C0Cns2 oe hold time t oeh 0C0C0Cns data-in setup time t ds 0C0C0Cns3 data-in hold time t dh 7 C 10 C 10 C ns 3 notes 1. t wp (min.) is applied to late write cycles or read modify write cycles. in early write cycles, t wch (min.) should be met. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. 3. t ds (min.) and t dh (min.) are referenced to the cas falling edge in early write cycles. in late write cycles and read modify write cycles, they are referenced to the we falling edge. read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit note min. max. min. max. min. max. read modify write cycle time t rwc 107 C 133 C 157 C ns ras to we delay time t rwd 64 C 77 C 89 C ns 1 cas to we delay time t cwd 27 C 32 C 37 C ns 1 column address to we delay time t awd 39 C 47 C 54 C ns 1 note 1. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate.
m PD42S17405L, 4217405l 13 hyper page mode (edo) parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit notes min. max. min. max. min. max. read / write cycle time t hpc 20 C 25 C 30 C ns 1 ras pulse width t rasp 50 125,000 60 125,000 70 125,000 ns cas pulse width t hcas 7 10,000 10 10,000 12 10,000 ns cas precharge time t cp 7 C 10 C 10 C ns access time from cas precharge t acp C30C35C40ns cas precharge to we delay time t cpwd 41 C 52 C 59 C ns 2 ras hold time from cas precharge t rhcp 30 C 35 C 40 C ns read modify write cycle time t hprwc 52 C 66 C 75 C ns data output hold time t dhc 5C5C5Cns oe to cas hold time t och 5C5C5Cns3 oe precharge time t oep 5C5C5Cns output buffer turn-off delay from we t wez 010013015ns4,5 we pulse width t wpz 7 C 10 C 10 C ns 5 output buffer turn-off delay from ras t ofr 010013015ns4,5 output buffer turn-off delay from cas t ofc 010013015ns4,5 notes 1. t hpc (min.) is applied to cas access. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. 3. we: inactive (in read cycle) cas: inactive, oe: active t cho is effective. cas, oe: active t och is effective. 4. t ofc (max.) , t ofr (max.) and t wez (max.) define the time when the output achieves the conditions of hi-z and is not referenced to v oh or v ol . 5. to make i/os to hi-z in read cycle, it is necessary to control ras, cas, we, oe as follows. the effective specification depends on state of each signal. (1) both ras and cas are inactive (at the end of the read cycle) we: inactive, oe: active t ofc is effective when ras is inactivated before cas is inactivated. t ofr is effective when cas is inactivated before ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both ras and cas are active or either ras or cas is active (in read cycle) we, oe: inactive t oez is effective. both ras and cas are inactive or ras is active and cas is inactive (at the end of read cycle) we, oe: active and either t rrh or t rch must be met t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective.
m PD42S17405L, 4217405l 14 refresh cycle parameter symbol t rac = 50 ns t rac = 60 ns t rac = 70 ns unit note min. max. min. max. min. max. cas setup time t csr 5C5C5Cns cas hold time (cas before ras refresh) t chr 10 C 10 C 10 C ns ras precharge cas hold time t rpc 5C5C5Cns ras pulse width (cas before ras self refresh) t rass 100 C 100 C 100 C m s1 ras precharge time (cas before ras self refresh) t rps 90 C 110 C 130 C ns 1 cas hold time (cas before ras self refresh) t chs C50 C C50 C C50 C ns 1 we setup time t wsr 10 C 10 C 10 C ns we hold time t whr 15 C 15 C 15 C ns note 1. this specification is applied only to the m PD42S17405L.
m PD42S17405L, 4217405l 15 read cycle t rc t ras t rp v ih v il ras t ofr hi - z t csh data out v ih v il cas v ih v il address v ih v il we v ih v il oe v oh v ol i/o hi - z t ofc t oez t clz t olz t cac t aa t rac t oea t wez t wpz t rrh t rcs row col. t cah t asc t rah t asr t rad t crp t rcd t rsh t cas t cpn t ral t rch t cho t oes t och
m PD42S17405L, 4217405l 16 early write cycle ras t ras t rc t rp t csh t rsh t rcd t cas t cpn t crp t rad t asr t rah t asc t cah row col. t wcs v ih v il cas v ih v il address v ih v il we v ih v il data in i/o v ih v il t ds t wch t dh remark oe: dont care
m PD42S17405L, 4217405l 17 late write cycle i/o ras v ih v il we v ih v il t ras t rp t rc cas v ih v il t csh t rcd t crp t rsh t cas t cpn address v ih v il t asr t rah t asc t cah t rad row col. t rcs oe v ih v il v ih v il t cwl t oed data in hi-z t rwl t wp t oeh t ds t dh
m PD42S17405L, 4217405l 18 read modify write cycle i/o ras v ih v il we v ih v il t ras t rp t rwc cas v ih v il t csh t rcd t crp t rsh t cas t cpn address v ih v il t asr t rah t asc t cah t rad row col. t rcs oe v ih v il v ih v il t rwd t cac data in t awd t cwd t ds t dh t wp t rwl t cwl t aa t rac t oed t oea t oeh i/o v oh v ol data out hi-z hi-z t oez t clz t olz
m PD42S17405L, 4217405l 19 hyper page mode (edo) read cycle ras cas address we oe i/o t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t rrh t wpz t wez t oez t acp t aa t cac t acp t aa t cac t dhc t dhc t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ofr t ofc t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 20 hyper page mode (edo) read cycle (we control) ras cas address we oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rasp t rp t crp t rcd t hcas t csh t rhcp t rsh t hcas t cpn t hcas t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rrh t wpz t ofr t ofc t oez t aa t aa t clz t cac t cac t clz t wez t wez t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z i/o t rch t wpz t rcs t rch t wpz t rcs t rch hi - z hi - z t wez t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 21 hyper page mode (edo) read cycle (oe control) t rasp t rhcp t rp t csh t hpc t rsh t ral t rad t asr t rah t asc t cah t asc t cah t asc t cah t rcs t rch t rrh t oea t oez t aa hi - z hi - z row col.a col.b col.c t oea t acp t oes t olz t crp t rcd t hcas t cp t hcas t cp t hcas t cpn ras cas address oe i/o data out a data out b data out b data out c t ofc t oez t ofr t oea t acp t och t olz t aa t cac t oez t oez t oep t oep t oep t och t och t cho t cho t cho we t rac t aa t cac t clz t cac t clz v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t olz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 22 hyper page mode (edo) early write cycle ras t rasp v ih v il cas v ih v il address v ih v il we v ih v il i/o v ih v il t rp t rhcp t rsh t hpc t cpn t csh t hcas t cp t hcas t hcas t cp t ral t cah t cah t asc t cah col. col. row t asr t rah t wcs t wcs t rcd t rad t asc col. t wch t wch t wch data in data in data in t dh t ds t dh t ds t dh t ds t wcs t asc t crp remarks 1. oe: dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 23 hyper page mode (edo) late write cycle cas v ih v il t cpn t cp t cp t csh t hcas t rcd ras v ih v il t rasp t rp t crp t hpc t rsh t rhcp t hcas t hcas row col. t asr t rah t rad t asc t cah t asc col. t cah t asc col. t cah t ral address v ih v il we v ih v il t rcs t cwl t wp t rcs t cwl t wp t rcs t cwl t wp t rwl oe v ih v il t oeh t oeh t oeh i/o v ih v il t oed t ds t dh hi-z data in t oed t ds t dh data in hi-z t oed t ds t dh data in hi-z remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 24 hyper page mode (edo) read modify write cycle remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle. t rcs cas v ih? v il? t cpn t cp t hcas t hcas t cp t hprwc t hcas t rcd ras v ih? v il? t rasp t rp t crp address v ih? v il? t asr t rah t rad t asc t cah t asc t cah t cah t asc row col. col. col. t ral we v ih? v il? t rwd t olz i/o v ih? v il? t dh t ds t awd t cwd t wp t rcs t cwl t acp t cpwd t awd t cwd t wp t cwl t acp t cpwd t awd t cwd t rcs t cwl t rwl t wp oe v ih? v il? i/o v oh? v ol? out t oez t clz t oed t oea t cac t aa t rac in t oea t oeh t cac t aa t olz t dh t ds out t oez t clz t oed in t olz t dh t ds out t oez t clz t oed in t oeh t aa t cac t oea t oeh hi-z hi-z hi-z hi-z
m PD42S17405L, 4217405l 25 hyper page mode (edo) read and write cycle v ih v il ras v ih v il cas v ih v il address v ih v il we v ih v il oe v oh v ol i/o t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t acp t aa t cac t wez t dhc t oea t rac t aa t cac t clz row col. col. col. data out data out hi - z t oez t wcs t wch hi - z t dh t ds data in i/o v ih v il t cho t olz t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m PD42S17405L, 4217405l 26 cas before ras self refresh cycle (only for the m PD42S17405L) remark address, oe : dont care i/o : hi-z ras cas we v ih _ v il _ v ih _ v il _ v ih _ v il _ t csr t wsr t whr t rass t rps t crp t rpc t chs t cpn cautions on use of cas before ras self refresh cas before ras self refresh can be used independently when used in combination with distributed cas before ras long refresh; however, when used in combination with burst cas before ras long refresh or with long ras only refresh (both distributed and burst), the following cautions must be observed. (1) normal combined use of cas before ras self refresh and burst cas before ras long refresh when cas before ras self refresh and burst cas before ras long refresh are used in combination, please perform cas before ras refresh 2,048 times within a 32 ms interval just before and after setting cas before ras self refresh. (2) normal combined use of cas before ras self refresh and long ras only refresh when cas before ras self refresh and ras only refresh are used in combination, please perform ras only refresh 2,048 times within a 32 ms interval just before and after setting cas before ras self refresh. (3) if t rass (min.) is not satisfied at the beginning of cas before ras self refresh cycles (t ras < 100 m s), cas before ras refresh cycles will be executed one time. if 10 m s < t ras < 100 m s, ras precharge time for cas before ras self refresh (t rps ) is applied. and refresh cycles (2,048/128 ms) should be met. for details, please refer to how to use dram users manual.
m PD42S17405L, 4217405l 27 cas before ras refresh cycle ras t rc v ih? v il? cas v ih? v il? t csr t chr t rpc t csr t chr t rpc t cpn t crp t ras t rp t rp t ras t rc v ih? v il? t whr t wsr we t whr t wsr remark address, oe: dont care i/o: hi-z ras only refresh cycle ras t rc v ih v il cas v ih v il t asr t crp t rpc t cpn t crp t ras t rp t rp t ras t asr t rc row address v ih v il t rah t rah row remark we, oe: dont care i/o: hi-z
m PD42S17405L, 4217405l 28 hidden refresh cycle (read) t rc t rc t ras t rp t rad t ral t asr t rah row col. data out hi - z hi - z t asc t rcs t whr t oes t oea t rac t aa t cac t olz t clz t ofc t oez t cah t rp t ras t crp t rcd t rsh t cpn t chr ras v ih v il cas v ih v il we v ih v il oe v ih v il i/o v oh v ol address v ih v il t wez t cho t ofr t wpz t rch
m PD42S17405L, 4217405l 29 hidden refresh cycle (write) ras t ras t rc t ras t chr t rcd t cpn t crp t rad t asc t cah row col. v ih? v il? cas v ih? v il? address v ih? v il? i/o t rp t rc t rp t rsh t asr t rah t ds t dh data in v ih? v il? we v ih? v il? t wcs t wch t wsr t whr remark oe: dont care
m PD42S17405L, 4217405l 30 test mode set cycle (we, cas before ras refresh cycle) ras v ih v il cas v ih v il we v ih v il t csr t chr t wsr t whr t rpc t crp t rc t ras t rp remark address, oe: dont care i/o: hi-z test mode by using the test mode, the test time can be reduced. the reason for this is that, the memory emulates the 16-bit organization during test mode. dont care about the input levels of the cas input a0, a1. (1) setting the mode executing the test mode cycle (we, cas before ras refresh cycle) sets the test mode. (2) write/read operation when either a 0 or a 1 is written to the input pin in test mode, this data is written to 16 bits of memory cell. next, when the data is read from the output pin at the same address, the cell can be checked. output = 1: normal write (all memory cells) output = 0: abnormal write (3) refresh refresh in the test mode must be performed with the ras / cas cycle or with the we, cas before ras refresh cycle. the we, cas before ras refresh cycle use the same counter as the cas before ras refreshs internal counter. (4) mode cancellation the test mode is cancelled by executing one cycle of ras only refresh cycle or cas before ras refresh cycle.
m PD42S17405L, 4217405l 31 package drawings item millimeters inches a b c e f g i 17.36 max. 1.27 (t.p.) 1.2 max. 0.97 1.06 max. m n 0.10 7.62?.1 0.21 0.1?.05 0.684 max. 0.042 max. 0.004?.002 0.048 max. 0.038 0.300?.004 0.009 0.004 0.050 (t.p.) a b n h 9.22?.2 0.363?.008 note each lead centerline is located within 0.21 mm (0.009 inch) of its true position (t.p.) at maximum material condition. g d 0.42 0.017?.003 j 0.8?.2 0.031 +0.009 ?.008 k 0.145 0.006?.001 l 0.5?.1 0.020 +0.004 ?.005 s26g3-50-7jd1 p3 +7 ? +0.025 ?.015 +0.08 ?.07 3 +7 ? m 26 14 113 c d m l k i h j f e p detail of lead end 26pin plastic tsop(ii) (300 mil)
m PD42S17405L, 4217405l 32 26 pin plastic soj (300 mil) item millimeters inches b 17.3 0.681 +0.008 ?.010 d 8.47?.2 0.333 +0.009 ?.008 e 1.03?.15 0.041 +0.006 ?.007 f g 3.5?.2 0.74 0.029 0.138?.008 s26la-300a-1 m 0.40?.10 0.016 +0.004 ?.005 c 7.62 0.300 h i 0.8 min. 2.545?.2 0.100?.008 0.031 min. j k 1.27 (t.p.) 2.6 0.102 0.050 (t.p.) u 0.20 0.008 +0.004 ?.002 n p 6.73?.2 0.12 0.005 0.265?.008 q t r0.85 0.10 0.004 r0.033 +0.20 ?.25 +0.10 ?.05 k m q m 26 14 j 113 e f i h g n b c d p t u note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition.
m PD42S17405L, 4217405l 33 recommended soldering conditions the following conditions (see tables below and next page) must be met for soldering conditions of the m PD42S17405L, 4217405l. for more details, refer to our document semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. types of surface mount device m PD42S17405Lg3-7jd, 4217405lg3-7jd: 26-pin plastic tsop (ii) (300 mil) soldering process soldering conditions infrared ray reflow peak temperature of package surface: 235 ?c or lower, reflow time: 30 seconds or less (210 ?c or higher), number of reflow processes: max. 3 exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) vps peak temperature of package: 215 ?c or lower, reflow time: 40 seconds or less (200 ?c or higher), number of reflow processes: max. 3 exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) partial heating method terminal temperature: 300 ?c or lower, time: 3 seconds or lower (per side of the package). note exposure limit before soldering after dry-pack package is opened. storage conditions: 25 ?c and relative humidity at 65 % or less. caution do not apply more than one soldering method at any one time, except for partial heating method. symbol ir35-107-3 vp15-107-3
m PD42S17405L, 4217405l 34 m PD42S17405Lla, 4217405lla: 26-pin plastic soj (300 mil) soldering process soldering conditions infrared ray reflow peak temperature of package surface: 235 ?c or lower, reflow time: 30 seconds or less (210 ?c or higher), number of reflow processes: max. 3 exposure limit: 7 days note (20 hours pre-baking is required at 125 ?c afterwards) vps peak temperature of package: 215 ?c or lower, reflow time: 40 seconds or less (200 ?c or higher), number of reflow processes: max. 3 exposure limit: 7 days note (20 hours pre-baking is required at 125 ?c afterwards) partial heating method terminal temperature: 300 ?c or lower, time: 3 seconds or less (per side of the package). note exposure limit before soldering after dry-pack package is opened. storage conditions: 25 ?c and relative humidity at 65 % or less. caution do not apply more than one soldering method at any one time, except for partial heating method. symbol ir35-207-3 vp15-207-3
m PD42S17405L, 4217405l 35 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m PD42S17405L, 4217405l 36 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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